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| this is information on a product in full production. september 2013 docid023145 rev 2 1/62 L99DZ81EP door actuator driver datasheet - production data features ? one full bridge for 6 a load (r on = 150 m ? ) ? one half bridges for 3 a load (r on = 300 m ? ) ? one configurable high-side driver for up to 1.5 a (r on = 500 m ? ) or 0.35 a (r on = 1600 m ? ) load ? one configurable high-side driver for 0.7 a (r on =800m ? ) or 0.35 a (r on = 1600 m ? ) load ? two high-side drivers for 0.5 a load (r on =1600m ? ) ? programmable softstart function to drive loads with higher inrush curren ts as current limitation value ? very low v s current consumption in standby mode (i s < 6 a typ; t j ? 85c) ? current monitor output for all high-side drivers ? central two-stage charge pump ? motor bridge driver with full r dson down to 6 v ? device contains temperature warning and protection ? open-load detection for all outputs ? overcurrent protection for all outputs ? separated half bridges for door lock motor ? programmable pwm control of all outputs ? stm standard serial peripheral interface (st-spi 3.1) ? prepared for additional fail-safe path for h-bridge applications ? door actuator driver with 3 bridges for double door lock control, 4 high-side drivers for bulbs and leds control. ? h-bridge control for exte rnal power transistors description the L99DZ81EP is a microcontroller driven multifunctional door actuator driver for automotive applications. up to two dc motors and four grounded resistive loads can be driven with three half bridges and four high-side drivers. four external mos transistors in bridge configuration can be driven. the integrated spi controls all operating modes (forward, reverse, brake and high impedance). also all diagnostic information is available via spi read. * $ 3 * & ) 7 tqfp-64 table 1. device summary package order codes tray tape and reel tqfp-64 L99DZ81EP L99DZ81EPtr www.st.com
contents L99DZ81EP 2/62 docid023145 rev 2 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4.1 tqfp-64 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 outputs out4 - out10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7 h-bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.8 spi / logic ? electrical charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1 dual power supply: vs and vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2 wake up and active mode/standby mode . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4 diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.5 overvoltage and undervoltage detection at vs . . . . . . . . . . . . . . . . . . . . 31 3.6 overvoltage and undervoltage detection at vcc . . . . . . . . . . . . . . . . . . . 31 3.7 temperature warning and shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.8 inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.9 open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.10 overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.11 current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.12 pwm mode of the power outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.13 cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.14 programmable soft-start function to drive loads with higher inrush current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.15 h-bridge control (dir, pwmh, bits sd, sds) . . . . . . . . . . . . . . . . . . . . . 34 3.16 h-bridge driver slew-rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.17 resistive low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 docid023145 rev 2 3/62 L99DZ81EP contents 4 3.18 short circuit detection/drain source monitoring . . . . . . . . . . . . . . . . . . . . 36 3.19 h-bridge monitoring in off-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.20 programmable cross current protection . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.21 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4 functional description of the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1.1 chip select not (csn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1.2 serial data in (di) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1.3 serial clock (clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1.4 serial data out (do) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1.5 spi communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.2 command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2.1 operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.3 device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5 spi - control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.1 control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.2 control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.3 control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.4 control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.5 control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.6 control register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.7 control register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.8 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.9 status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.10 status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.11 status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.12 status register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.1 ecopack ? package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.2 tqfp-64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3 tqfp-64 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 contents L99DZ81EP 4/62 docid023145 rev 2 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 docid023145 rev 2 5/62 L99DZ81EP list of tables 5 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. package thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 8. supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9. overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 10. current monitor output (cm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 11. charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 12. on-resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 13. power outputs switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 14. current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 15. gate drivers for the external power-mos (h-bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 16. gate drivers for the external power-mos switching times . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 17. drain source monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 18. open-load monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 19. delay time from standby to acti ve mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 20. inputs: di, csn, clk, dir and pwmh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 21. ac-characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 22. dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 23. watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 24. h-bridge control truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 25. h-bridge ds-monitor threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 26. cross-current protection time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 27. command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 28. operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 29. ram memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 30. rom memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 31. global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 32. control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 33. control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 34. control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 35. control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 36. control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 37. control register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 38. control register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 39. configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 40. status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 41. status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 42. status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 43. status register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 44. tqfp-64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 45. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 list of figures L99DZ81EP 6/62 docid023145 rev 2 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3. tqfp-64 2 layer pcb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4. tqfp-64 4 layer pcb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. tqfp-64 thermal impedance junction to ambient vs pcb copper area . . . . . . . . . . . . . . . 14 figure 6. ighxr ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 7. ighxf ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8. h-driver delay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9. spi timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 10. spi input and output timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 figure 11. spi delay description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 12. power-output (out<10:4>) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 13. overcurrent recovery mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 14. h-bridge gshx slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 15. h-bridge diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 16. h-bridge open-load detection (no open-load detecte d) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 17. h-bridge open-load detection (open-load detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 18. h-bridge open-load detection (short to ground det ected) . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 19. h-bridge open-load detection with h-olth high = ?1? (short to v s detected) . . . . . . . . . 39 figure 20. write and read spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 21. tqfp-64 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 22. tqfp-64 power lead-less tray shipment (no suffix) (part 1) . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 23. tqfp-64 power lead-less tray shipment (no suffix) (part 2) . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 24. tqfp-64 power lead-less tape and reel shipme nt (suffix ?tr?) (part 1). . . . . . . . . . . . . . . 59 figure 25. tqfp-64 power lead-less tape and reel shipme nt (suffix ?tr?) (part 2). . . . . . . . . . . . . . . 60 docid023145 rev 2 7/62 L99DZ81EP block diagram and pin description 61 1 block diagram and pin description figure 1. block diagram driver interface, logic & diagnostic spi interface to watchdog charge pump cm csn clk do di vcc v bat spc560d gnd 1k cm mux 1k 1k 1k 1k cp m m out4 out5 out6 out9 out7 out8 m 150 m 150 m 300 m 1600 m 1600 out10 m 1600 / 500 cp1m cp1p cp2m cp2p vs 2 x m gh1/2 sh1/2 gl1/2 sl1/2 pwmh m 1600 / 800 dir 1k 1k l99pm62 fso spi window watchdog => fail safe 100 10 watt bulb 5 watt bulb spi adjustable slew rate ~ 100nf ~ 100nf ~ 100nf >15 >15 >15 >15 fail safe circuitry > 10k gapgcft00674 table 2. pin definitions and functions pin symbol function 58 gnd 1 ground: reference potential. g nd1 and gnd2 are internally connected. gnd2 supplies out4-6. important: for the capability of drivin g the full current at the outputs, all pins of gnd must be externally connected! 17, 18, 26, 31, 32 gnd 2 17, 57 sgnd signal ground: this pin is shared with gnd2 pin. block diagram and pin description L99DZ81EP 8/62 docid023145 rev 2 2, 46, 51, 52 vs 1 power supply voltage for power stage outputs (external reverse protection required): for this input a ceramic capacitor as close as possible to gnd is recommended. vs1 supplies out7-10 and the internal vs supply, vs2 supplies out4-6. important: for the capability of drivin g the full current at the outputs all pins of vs must be externally connected! 11, 12, 23, 36, 37 vs 2 19, 20, 21, 22 out4 half-bridge ou tputs 4,5,6: the output is built by a high side and a low side switch, which are internally connected. the output stage of both switches is a power dmos transistor. each driver has an internal parasitic reverse diode (bulk-drain-di ode: high side driver from output to vs, low side driver from gnd to output). this output is over current and open load protected. 27, 28, 29, 30 out5 24, 25 out6 40 do serial data output: the diagnosis data is available via the spi and this 3-state-output. the out put remains in 3-state, if the chip is not selected by the input csn (csn = high). 34 cm current monitor output: depending on the selected multiplexer bits of the control register this output sources an image of the instant current through the corresponding high side driver with a fixed ratio. 35 csn chip-select-not input: this input is low active and requires cmos logic levels. the serial data transfer between the device and the micro controller is enabled by pulling the input csn to low level. 41 di serial data input: the input requires cmos logic levels and receives serial data from the microcontroller. the data is a 24 bit control word and the most significant bit (msb, bit 23) is transferred first. 38 clk serial clock input: this input controls the internal shift register of the spi and requires cmos logic levels. 33 dir direction input: this input controls the h-bridge drivers. 39 vcc supply voltage: 5 v supply. a ceramic capacitor as close as possible to gnd is recommended. 44 out9 high-side-driver output 9: the output is built by a high side switch and is intended for resistive loads; hence the internal reverse diode from gnd to the output is missing. fo r esd reason a diode to gnd is present but the energy which can be dissipated is limited. the high- side driver is a power dmos transistor with an internal parasitic reverse diode from the output to vs (bulk-drain-diode). the output is over current and open load protected. 42 pwmh pwmh input: this input signal can be used to control the h-bridge gate drivers. 3, 43, 45, 48, 49, 50, 53, 54, 55, 56, 59, 60 nc not connected. 62, 63 out7 high side driver output 8: see out9. important: this output ca n be configured to supply a bulb with low on- resistance or a led with higher on-resistance in a different application. 61 out8 47 out10 high-side-driver-output 10: see out9. table 2. pin definitions and functions (continued) pin symbol function docid023145 rev 2 9/62 L99DZ81EP block diagram and pin description 61 13 gh2 gh2: gate driver for power mos high side switch in half-bridge 2. 14 sh2 sh2: source of high-side switch in half-bridge 2. 15 gl2 gl2: gate driver for power mos low side switch in half-bridge 2. 16 sl2 sl2: source of low side switch in half-bridge 2. 64 gh1 gh1: gate driver for power mos high side switch in half-bridge 1. 1 sh1 sh1: source of high-side switch in half-bridge 1. 4 gl1 gl1: gate driver for power mos low side switch in half-bridge 1. 5 sl1 sl1: source of low side switch in half-bridge 1. 7 cp1p cp1p: charge pump pin for capacitor 1, positive side. 8 cp1m cp1m: charge pump pin for capacitor 1, negative side. 9 cp2p cp2p: charge pump pin for capacitor 2, positive side. 10 cp2m cp2m: charge pump pin for capacitor 2, negative side. 6 cp cp: charge pump output. table 2. pin definitions and functions (continued) pin symbol function block diagram and pin description L99DZ81EP 10/62 docid023145 rev 2 figure 2. pin connection (top view) cp1p cp1m cp2p cp2m cp cm dir csn vs 2 vs 2 gh2 sh2 gl2 sl2 gnd 2 /sgnd gnd 2 out4 out4 out4 out4 vs 2 out6 out6 gnd 2 out5 out5 out5 out5 gnd 2 gnd 2 out10 vs 1 nc out9 nc pwmh di do vcc clk vs 2 vs 2 out7 out7 out8 nc nc gnd 1 sgnd vs 1 nc nc nc nc vs 1 nc nc nc tqfp64 64 sh1 vs 1 nc gh1 gl1 sl1 1 16 17 32 33 48 49 gapgcft00673 docid023145 rev 2 11/62 L99DZ81EP electrical specifications 61 2 electrical specifications 2.1 absolute maximum ratings stressing the device above the rating listed in table 3 may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specif ication is not implied. exposure to absolute maximum rating condit ions for extended periods may affect device reliability. table 3. absolute maximum ratings symbol parameter/test condition value [dc voltage] unit v s1 , v s2 dc supply voltage -0.3 to +28 v single pulse / t max < 400 ms ?transient load dump? -0.3 to +40 v v cc stabilized supply voltage, logic supply -0.3 to v s +0.3 v v di, v clk , v csn , v do , v cm , v dir , v pwmh , v dir logic input / output voltage range -0.3 to v cc +0.3 v v outn output voltage (n = 4 to 10) -0.3 to v s +0.3 v v sl1 , v sh1 , v sl2 , v sh2 (v sxy ) high voltage signal pins -6 to 40 v v gl1 , v gh1 , v gl2 , v gh2 (v gxy ) high voltage signal pins v sxy - 1 to v sxy +10; v cp +0.3 v v cp1p high voltage signal pins v s - 0.3 to v s +10 v v cp2p high voltage signal pins v s - 0.6 to v s +10 v v cp1m , v cp2m high voltage signal pins -0.3 to v s +0.3 v v cp high voltage signal pin v s1,2 ?? 26 v v s - 0.3 to v s +14 v v s1,2 > 26 v v s - 0.3 to +40 v i out9,10 output current (1) 1.25 a i out6,7 output current (1) (low on-resistance mode) 5 a i out7 output current (1) (high on-resistance mode) 5 a i out8 output current (1) 2.5 a i out4,5 output current (1) 10 a i vs1cum maximum cumulated i nput current at vs 1 pins (1) 12.5 a i vs2cum maximum cumulated i nput current at vs 2 pins (1) 12.5 a i gnd1cum maximum cumulated output current at gnd 1 pins (1) 5 a i gnd2cum maximum cumulated output current at gnd 2 pins (1) 12.5 a 1. values for the absolute maximum dc current through the bon d wires. this value does not consider maximum power dissipation or other limits. electrical specifications L99DZ81EP 12/62 docid023145 rev 2 2.2 esd protection 2.3 thermal data table 4. esd protection parameter value unit all pins 2 (1) 1. hbm according to mil 883c, method 3015.7 or eia/jesd22-a114-a. kv power output pins: out4 ? out10 4 (1) kv table 5. operating junction temperature symbol parameter value unit t j operating junction temperature -40 to 150 c table 6. temperature warning and thermal shutdown symbol parameter test condition min. typ. max. unit t jtw on temperature warning threshold (junction temperature) 130 150 c t jts on thermal shutdown threshold (junction temperature) 150 170 c t jtft thermal warning / shutdown filter time 32 s table 7. package thermal impedance symbol parameter value unit r thj-amb thermal resistance junction to ambient (max) see figure 5 k/w docid023145 rev 2 13/62 L99DZ81EP electrical specifications 61 2.4 package and pcb thermal data 2.4.1 tqfp-64 thermal data figure 3. tqfp-64 2 layer pcb figure 4. tqfp-64 4 layer pcb note: layout condition of r th and z th measurements (board finish thickness 1.6 mm +/- 10%, board double layer and four layers, board di mension 77 mm x114 mm, board material fr4, cu thickness 0.070mm (outer la yers), cu thickness 0.035mm (inner layers), thermal vias separation 1.2 mm, thermal via diameter 0. 3 mm +/- 0.08 mm, cu thickness on vias 0.025 mm, footprint dimension 6 mm x 6 mm). 4-layer pcb: cu on mid1 layer, cu on mid2 layer and cu on bottom layer: 62 cm 2 . z th measured on the major power dissipator contributor * $ 3 * & ) 7 * $ 3 * & ) 7 electrical specifications L99DZ81EP 14/62 docid023145 rev 2 figure 5. tqfp-64 thermal impedance junction to ambient vs pcb copper area docid023145 rev 2 15/62 L99DZ81EP electrical specifications 61 2.5 electrical characteristics the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v ? v s ? 18 v, 4.75 v ? v cc ? 5.5 v; all outputs open; t j = -40 c to 150 c, unless otherwise specified. table 8. supply symbol parameter test condition min. typ. max. unit v s operating voltage range 5 28 v i vs(act) current consumption in active mode v s =13.5v (1) 1. this parameter is guaranteed by design 510ma i vs(stby) current consumption in standby mode v s =16v; v cc =5.3v; standby mode; out4 - out10 floating; t test = -40 c to 25 c 412a t test =85c (1) 625a v cc operating voltage range 4.5 5.5 v i vcc(active) v cc supply current v s =16v; v cc =5.3v; csn = v cc ; active mode; out4 - out10 floating 510ma i vcc(stby) v cc standby current v s =16v; v cc =5.0v; csn = v cc ; active mode; out4 - out10 floating; t test = -40 c to 25 c 36a t test =85c (1) 48a v s =16v; v cc =5.3v; csn = v cc ; active mode; out4 - out10 floating; t test = -40 c to 125 c 25 a table 9. overvoltage and undervoltage detection symbol parameter test condition min. typ. max. unit v suv on vs uv threshold voltage (1) v s increasing 5.6 7.2 v v suv off vs uv threshold voltage (1) v s decreasing 5 5.9 v v suv hyst vs uv hysteresis (1) v suv on -v suv off 0.5 v t vsuvfilt vs uv filter time 48 s v sov off vs ov threshold voltage (1) v s increasing 18.5 24.5 v v sov on vs ov threshold voltage (1) v s decreasing 18.0 23.5 v v sov hyst vs ov hysteresis (1) v sov off -v sov on 1v t vsovfilt vs ov filter time 48 s v vccreshu upper v cc reset threshold (2) v cc increasing 5.8 7.5 v electrical specifications L99DZ81EP 16/62 docid023145 rev 2 v vccreshd upper v cc reset threshold v cc decreasing 5.5 7.1 v v vccres hysth upper reset hysteresis v vccreshu - v vccreshd 0.1 v v poroff power-on-reset threshold v cc increasing 3.4 4.4 v v poron power-on-reset threshold v cc decreasing 3.1 4.1 v v por hystl power-on-reset hysteresis v poroffl - v poronl 0.3 v 1. vs = 5v to 28v 2. if v cc exceeds this value all registers are reset and the device enters standby mode. table 9. overvoltage and undervoltage detection (continued) symbol parameter test condition min. typ. max. unit table 10. current monitor output (cm) symbol parameter test condition min. typ. max. unit v cm functional voltage range 0 v cc -1v v i cm r current monitor output ratio: i cm /i out4,5,6,7 (low on-resistance) 0v ? v cm ? v cc -1v 1/10000 i cm /i out8 (low on-resistance) 1/6500 i cm /i out7,8,9,10 and 7,8 (high on- resistance) 1/2000 i cm acc current monitor accuracy acci cmout4,5,6 and 7(low on-resistance) 0v ? v cm ? v cc -1v; i outmin =500ma; i out4,5max =5.9a; i out6max =2.9a; i out7max =1.4a 4% + 1%fs (1) 8% + 2%fs (1) acci cmout7,8,9,10(high on-resistance 0v ? v cm ? v cc -1v; i out.min =100ma; i out9,10max =0.4a; i out7max =0.3a; i out8(low rdson)max =0.6a; i out8(high rdson)max =0.3a t cmb current monitor blanking time 32 s 1. fs (full scale) = i outmax *i cmr table 11. charge pump symbol parameter test condition min. typ. max. unit v cp charge pump output voltage v s =6v; i cp =-10ma v s +6 v s +7 v s +7.85 v v s ? 10 v; i cp =-15ma v s +11 v s +12 v s +13.5 v i cp charge pump output current (1) v cp =v s +10v; v s =13.5v; c 1 =c 2 =c cp = 100 nf 25 47 ma i cplim charge pump output current limitation (2) v cp =v s ; v s =13.5v; c 1 =c 2 =c cp = 100 nf 29 70 ma docid023145 rev 2 17/62 L99DZ81EP electrical specifications 61 2.6 outputs out4 - out10 the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v ? v s ? 18 v, 4.75 v ? v cc ? 5.5 v; all outputs open; t j = -40c to 150c, unless otherwise specified. v cp_low charge pump low threshold voltage v s +4.6 v s +5 v s +5.4 v t cp charge pump low filter time 64 s 1. i cp is the minimum current the device can pr ovide to an external circuit without v cp going below v s +10v 2. i cplim is the maximum current, which flows out of the device in case of a short to v s table 11. charge pump (continued) symbol parameter test condition min. typ. max. unit table 12. on-resistance symbol parameter test condition min. typ. max. unit r on out4,5 on-resistance to supply or gnd v s =13.5v; t amb =+25c; i out4,5 =3.0a 150 200 m ? v s =13.5v; t amb = +125 c; i out4,5 =3.0a 225 300 m ? r on out6 on-resistance to supply or gnd v s =13.5v; t amb =+25c; i out6 =1.5a 300 400 m ? v s =13.5v; t amb = +125 c; i out6 =1.5a 450 600 m ? r on out7 on-resistance to supply in low resistance mode v s =13.5v; t amb =+25c; i out7 =-0.8a 500 700 m ? v s =13.5v; t amb = +125 c; i out7 =-0.8a 700 950 m ? on-resistance to supply in high resistance mode v s =13.5v; t amb =+25c; i out7 =-0.2a 1600 2400 m ? v s =13.5v; t amb = +125 c; i out7 =-0.2a 2500 3400 m ? r on out8 on-resistance to supply in low resistance mode v s =13.5v; t amb =+25c; i out8 =-0.4a 800 1200 m ? v s =13.5v; t amb = +125 c; i out8 =-0.4a 1200 1700 m ? on-resistance to supply in high resistance mode v s =13.5v; t amb =+25c; i out8 =-0.2a 1600 2400 m ? v s =13.5v; t amb = +125 c; i out8 =-0.2a 2500 3400 m ? electrical specifications L99DZ81EP 18/62 docid023145 rev 2 r on out9,10 on-resistance to supply v s =13.5v; t amb =+25c; i out9,10 =-0.4a 1600 2200 m ? v s =13.5v; t amb = +125 c; i out9,10 =-0.4a 2500 3400 m ? i qlh switched-off output current high side drivers of out 4,6,9,10 v out = 0 v; standby mode -5 -2 a v out = 0 v; active mode -10.2 -7 a i qlh7,8 switched-off output current high side drivers of out 7,8 v out = 0 v; standby mode -5 -2 a v out = 0 v; active mode -15 -10 a i qll switched-off output current low side drivers of out 4-6 v out =v s ; standby mode 80 165 a v out =v s -0.5v; active mode -10 -7 a table 13. power outputs switching times symbol parameter test condition min. typ. max . unit t d on h output delay time high side driver on (all out except out 7,8 ) v s =13.5v; v cc =5v; corresponding low side driver is not active (1)(2)(3) 1. r load = 16 ? at out 6 and out 7,8 in low on-resistance mode 10 40 80 s output delay time high side driver on (out 7,8 in high r dson mode) 15 35 60 s output delay time high side driver on (out 7,8 in low r dson mode) 10 35 80 s t d off h output delay time high side driver off (out 4,5,6 ) v s =13.5v; v cc =5v (1)(2)(3) 50 150 300 s output delay time high side driver off (out 7,8,9,10 ) 40 70 100 s t d on l output delay time low side driver on v s =13.5v; v cc =5v; corresponding low side driver is not active (1)(2)(3) 15 30 70 s t d off l output delay time low side driver (out 4-6 ) off v s =13.5v; v cc =5v (1)(2)(3) 40 150 300 s t d hl cross current protection time (out 4-6 ) t cc onls_offhs ? t doffh (4) 40 200 400 s t d lh t cc onhs_offls ? t doffl (4) dv out /dt slew rate of outx v s =13.5v; v cc =5v (1)(2)(3) 0.08 0.2 0.6 v/s f pwmx(low) low pwm switching frequency v s =13.5v; v cc = 5 v 122 hz f pwmx(high) high pwm switching frequency v s =13.5v; v cc = 5 v 244 hz table 12. on-resistance (continued) symbol parameter test condition min. typ. max. unit docid023145 rev 2 19/62 L99DZ81EP electrical specifications 61 2. r load = 4 ? at out 4,5 3. r load = 64 ? at out 9,10 and out 7,8 in high on-resistance mode 4. t cc is the switch-on delay time if complement in half bridge has to switch off table 14. current monitoring symbol parameter test condition min. typ. max. unit |i oc4 |, |i oc5 | overcurrent threshold to supply or gnd v s =13.5v; v cc = 5 v; sink and source 69.2a |i oc6 |35.3a |i oc7 | overcurrent threshold to supply in low on-resistance mode v s =13.5v; v cc =5v; source 1.5 2.5 a overcurrent threshold to supply in high on-resistance mode 0.35 0.65 a |i oc8 | overcurrent threshold to supply in low on-resistance mode 0.7 1.3 a overcurrent threshold to supply in high on-resistance mode 0.35 0.65 a |i oc9 |, |i oc10 | overcurrent threshold to supply 0.5 1.0 a t foc filter time of overcurrent signal duration of overcurrent condition to set the status bit 10 55 100 s f rec0 recovery frequency for oc; recovery frequency bit = 0 1 4 khz f rec1 recovery frequency for oc; recovery frequency bit = 1 2 6 khz |i old4 |, |i old5 | undercurrent threshold to supply or gnd v s =13.5v; v cc =5v; sink and source 60 150 300 ma |i old6 |83080ma |i old7 | undercurrent threshold to supply in low on-resistance mode v s =13.5v; v cc =5v; source 15 40 60 ma undercurrent threshold to supply in high on-resistance mode 51015ma |i old8 | undercurrent threshold to supply in low on-resistance mode 10 30 45 ma undercurrent threshold to supply in high on-resistance mode 51015ma |i old9 |, |i old10 | undercurrent threshold to supply 10 20 30 ma t fol filter time of open-load signal duration of open- load condition to set the status bit 0.5 2.0 3.0 ms electrical specifications L99DZ81EP 20/62 docid023145 rev 2 2.7 h-bridge driver table 15. gate drivers for the external power-mos (h-bridge) symbol parameter test condition min. typ. max. unit drivers for external high-side power-mos i ghx(ch) average charge current (charge stage) t j =25c 0.3 a r ghx on-resistance (discharge- stage) v shx =0v; i ghx =50ma; t j =25c 468 ? v shx =0v; i ghx =50ma; t j =125c 810 ? v ghxh gate-on voltage outputs floating v shx + 8 v shx + 10 v shx + 11.5 v r gshx passive gate-clamp resistance v ghx =0.5v 15 k ? drivers for external low-side power-mos i glx(ch) average charge-current (charge stage) t j =25c 0.3 a r glx on-resistance (discharge- stage) v slx =0v; i ghx =50ma; t j =25c 468 ? v slx =0v; i ghx =50ma; t j =125c 810 ? v ghlx gate-on voltage outputs floating v slx + 8 v slx + 10 v slx + 11.5 v r gslx passive gate-clamp resistance 15 k ? table 16. gate drivers for the external power-mos switching times symbol parameter test condition min. typ. max. unit t g(hl)xhl propagation delay time high to low (switch mode) (1) v s = 13.5 v; v shx =0; r g =0 ? ; c g =2.7nf 1.5 s t g(hl)xlh propagation delay time low to high (switch mode) (1) v s = 13.5 v; v slx =0; r g =0 ? ; c g =2.7nf 1.5 s i ghxrmax maximum charge current (current mode) v s = 13.5 v; v shx =0; v ghx =1v; slew < 4:0 ? 1f h 24.5 31 38.5 ma i ghxfmax maximum discharge current (current mode) v s = 13.5 v; v shx =0; v ghx =2v; slew < 4:0 ? 1f h 18.5 25 33 ma di ighxr charge current accuracy v s = 13.5 v; v shx =0; v ghx =1v see figure 6 di ighxf discharge current accuracy v s = 13.5 v; v shx =0; v ghx =2v see figure 7 docid023145 rev 2 21/62 L99DZ81EP electrical specifications 61 v dshxrsw switching voltage (v s -v sh ) between current mode and switch mode (rising) v s = 13.5 v 1.5 v v tdshxf (2) trigger voltage to sample the v gsh for switching between switch mode and current mode (falling) v s = 13.5 v; v ghx =4v 1.5 v v tgshxacc (2) sampled trigger voltage accuracy v s = 13.5 v; v shx =0 1 v t0 ghxr rise time (switch mode) v s = 13.5 v; v shx =0; r g =0 ? ; c g =2.7nf 45 ns t0 ghxf fall time (switch mode) v s = 13.5 v; v shx =0; r g =0 ? ; c g =2.7nf 85 ns t0 glxr rise time v s = 13.5 v; v slx =0; r g =0 ? ; c g =2.7nf 45 ns t0 glxf fall time v s = 13.5 v; v slx =0; r g =0 ? ; c g =2.7nf 85 ns t ccp programmable cross-current protection time 0.1 5 s f pwmh pwmh switching frequency (1) v s = 13.5 v; v slx =0; r g =0 ? ; c g =2.7nf; pwmh - duty cycle = 50 % 50 khz 1. without cross-current protection time t ccp 2. parameter not tested, typical value validated by characterization. table 16. gate drivers for the external power-mos switching times symbol parameter test condition min. typ. max. unit electrical specifications L99DZ81EP 22/62 docid023145 rev 2 figure 6. ighxr ranges figure 7. ighxf ranges ' ! 0 ' # & 4 c u r r r e n t i n m ! d a t a i n p u t ) ' ( x r a c c u r a c y ) ' ( x r - a x ) ' ( x r 4 y p ) ' ( x r - i n ' ! 0 ' # & 4 c u r r e n t i n m ! d a t a i n p u t ) ' ( x f a c c u r a c y ) ' ( x f - a x ) ' ( x f 4 y p ) ' ( x f - i n docid023145 rev 2 23/62 L99DZ81EP electrical specifications 61 figure 8. h-driver delay times 9 * 6 + / [ w 9 & 6 1 3 : 0 + ' , 5 w w 9 & 6 1 3 : 0 + ' , 5 7 * + / [ / + 7 * + / [ + / * $ 3 * & ) 7 table 17. drain source monitoring symbol parameter test condition min. typ. max. unit v scd1 drain-source threshold voltage v s = 13.5 v 0.3 0.5 0.7 v v scd2 drain-source threshold voltage v s = 13.5 v 0.8 1 1.2 v v scd3 drain-source threshold voltage v s = 13.5 v 1.2 1.5 1.8 v v scd4 drain-source threshold voltage v s = 13.5 v 1.6 2 2.4 v t scd drain-source monitor filter time 3 5.5 8 s t scs drain-source comparator settling time v s = 13.5 v; v sh = jump from gnd to v s ? 5s electrical specifications L99DZ81EP 24/62 docid023145 rev 2 table 18. open-load monitoring symbol parameter test condition min. typ. max. unit v odsl low-side drain-source monitor low off-threshold voltage v slx =0v; v s = 13.5 v 0.14 * v s 0.18 * v s 0.21 * v s v v odsh low-side drain-source monitor high off-threshold voltage v slx =0v; v s = 13.5 v 0.75 * v s 0.85 * v s 0.95 * v s v v olshx output voltage of selected shx in open-load test mode v slx =0v; v s =13.5v 0.5*v s v r pdol pull-down resistance of the non- selected shx pin in open-load mode v slx =0v; v s =13.5v; v shx =4.5v 20 k ? t ol open-load filter time 2 ms docid023145 rev 2 25/62 L99DZ81EP electrical specifications 61 2.8 spi / logic ? elect rical characteristics the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6v ? v s ? 18 v, 4.75 v ? v cc ? 5.5 v; all outputs open; t j = -40 c to 150 c, unless otherwise specified. table 19. delay time from standby to active mode symbol parameter test condition min typ max unit t set delay time switching time from standby to active mode. time until output drivers are enabled after csn going to high and set bit 0 = 1 of control register 0. 250 310 410 s t wakup wake-up time switching from standby to active mode. time after the first falling edge of csn until the first positive clk edge, which latches en = 1 correctly into the device ?20s t awake stay awake time switching from standby to active mode. after the first rising edge of csn a second spi frame with en = 1 is correctly recognized ? 256 s table 20. inputs: di, cs n, clk, dir and pwmh symbol parameter test condition min typ max unit inputs: csn, clk, di, dir, pwmh v il input voltage low level v s = 13.5 v; v cc =5.0v 0.3*v cc v v ih input voltage high level v s = 13.5 v; v cc =5.0v 0.7*v cc v v ihys input hysteresis v s = 13.5 v; v cc =5.0v 500 mv r csn in csn pull-up resistor v s = 13.5 v; v cc =5.0v; 0v ? v csn ? 0.7 * v cc 60 110 215 k ? r clk in clk pull-down resistor v s = 13.5 v; v cc =5.0v; 0.3 * v cc ? v clk ? v cc 60 110 215 k ? r di in di pull-down resistor v s = 13.5 v; v cc =5.0v; 0.3 * v cc ? v di ? v cc 60 110 215 k ? r dir dir pull-down resistor v s = 13.5 v; v cc =5.0v; 0.3 * v cc ? v dir ? v cc 60 110 215 k ? r pwmh pwmh pull-down resistor v s = 13.5 v; v cc =5.0v; 0.3 * v cc ? v pwmh ? v cc 60 110 215 k ? output: do v ol output voltage low level i ol =5ma; v s = 13.5 v; v cc =5.0v 0.3 * v cc v v oh output voltage high level i oh =-5ma; v s = 13.5 v; v cc =5.0v 0.7 * v cc v i dolk 3-state leakage current v csn =v cc ; 0 < v do docid023145 rev 2 27/62 L99DZ81EP electrical specifications 61 figure 9. spi timing parameters t r in rise time of input signal di, clk, csn v s = 13.5 v; v cc =5v 100 ns t f in fall time of input signal di, clk, csn v s = 13.5 v; v cc =5v 100 ns table 22. dynamic characteristics (continued) symbol parameter test condition min. typ. max. unit * $ 3 * 0 6 & 6 1 ' 2 ' d w d r x w & / . ' d w d r x w ' d w d l q ' d w d l q ' , w 6 & / . w / & / . w + & / . w & / . 4 9 w & 6 1 4 7 w + & 6 1 w 6 ' , w 6 & 6 1 w & 6 1 4 9 electrical specifications L99DZ81EP 28/62 docid023145 rev 2 figure 10. spi input and output timing parameters figure 11. spi delay description ' 2 o r z w r k l j k 9 & & w u ' 2 ' 2 k l j k w r o r z ' , & / . & 6 1 * $ 3 * 0 6 w i ' 2 9 & & 9 & & 9 & & 9 & & 9 & & w i l q w u l q 0 l f u r & r q w u r o o h u 0 d v w h u 6 o d y h 6 & . 0 , 6 2 * $ 3 * 0 6 w 6 & . u l v h w 6 & . i l o w w 6 & . 4 9 w v h w x s docid023145 rev 2 29/62 L99DZ81EP electrical specifications 61 figure 12. power-output (out<10:4>) timing table 23. watchdog symbol parameter test condition min. typ. max. unit tc wdto watchdog time out 50 64 100 ms * $ 3 * 0 6 w u l q w & 6 1 b + , p l q w i l q & 6 1 w g 2 ) ) w 2 ) ) w g 2 1 w 2 1 2 x w s x w y r o w d j h r i d g u l y h u 2 x w s x w y r o w d j h r i d g u l y h u 2 1 v w d w h 2 ) ) v w d w h 2 1 v w d w h 2 ) ) v w d w h & 6 1 o r z w r k l j k g d w d i u r p v k l w u h j l v w h u l v w u d q v i h u u h g w r r x w s x w s r z h u v z l w f k h v application information L99DZ81EP 30/62 docid023145 rev 2 3 application information 3.1 dual power supply: v s and v cc the power supply voltage v s supplies the power drivers and the power-mos gate drivers. for supplying the high-side drivers for the power- and gate-driver outputs, an internal charge-pump is used. the spi interface an d the logic circuitry is supplied by v cc . due to the independent v cc supply the control and status in formation are not lost, if there are spikes or glitches on the power supply voltage. 3.2 wake up and acti ve mode/standby mode after power up of v s and v cc the device operates in st andby-mode. pulling the signal csn to low level wakes the device up and the analog part is activated (active mode). after at least 10 s, the first spi commun ication is valid and the en-bit can be used to set the en- mode. the device can be set into active mode writing a ?1? into the en-register. if the en-register is not set to ?1?, the device goes back to standby mode typical 256 s after the rising edge of csn and all latched data are cleared. in standby mode the current at v s (v cc ) is less than 6 a (5 a) for csn = high (do in 3-state). it is recommended to switch all outputs off before entering standby mode. 3.3 charge pump the charge pump uses two external capaci tors, which are switched with a frequency of typically 125 khz. the output of the charge pum p has a current limitation. in standby mode and after a thermal shutdown has been triggered the charge pump is disabled. if the charge pump output voltage remains too low for longer than t cp , the power-mos outputs, the ec- control are switched off and the h-bridge gate drivers are switched to resistive low. the cp_low bit has to be cleared through a so ftware reset to reac tivate the drivers. 3.4 diagnostic functions all diagnostic functions (overc urrent, open-load, power supply overvoltage /undervoltage, temperature warning and thermal shutdown) are in ternally filtered. the condition has to be valid for at least the associated filter time before the corresponding status bit in the status registers is set. the filters are used to improve the noise immunity of the device. the open- load and temperature warning functions are intended for information purpose and do not change the state of the output drivers. on contrary, the overcurrent condition disables the corresponding driver and thermal shutdown disables all drivers. without setting the overcurrent recovery bits in the input data register, the microcontroller has to clear the overcurrent status bits to reactivate the corresponding drivers. docid023145 rev 2 31/62 L99DZ81EP application information 61 3.5 overvoltage and underv oltage detection at v s if the power supply voltage v s rises above the overvoltage threshold v sov_off , the outputs out4 to out10 are switched to high impedance state, the charge pump is disabled and the h-bridge gate drivers are switched into sink condition to protect the h-bridge and the load. when the voltage v s drops below the undervoltage threshold v suv_off (uv-switch-off voltage), the output stages are switched to hi gh impedance to avoid the operation of the power devices without sufficient gate driving voltage (increased power dissipation). if the supply voltage v s recovers to normal operating voltage, the charge pump is switched on again, the cp_low bit is cleared and the output stages return to the programmed state. if the undervoltage/overvoltage recovery disable bi t is set, the automatic turn-on of the drivers is deactivated. if the undervoltage/overvoltage recovery disable bit (ov_uv_rd) is set, the microcontroller needs to clear the status bits to reactivate the drivers. it is recommended to set ov_uv_rd bit to avoid a possible high current oscillation in case of a shorte d output to gnd and low battery voltage. 3.6 overvoltage and underv oltage detection at v cc at power-on (v cc increases from undervoltage to v poroff ) the circuit is initialized by an internally generated power-on-reset (por). if the voltage v cc decreases below the low threshold (v poron ), the outputs are switched to 3-state (high impedance) and the status registers are cleared. if the voltage at pin v cc increases above the v cc reset high threshold v vccreshu , the device enters the reset state, all outputs are switched off and all internal registers are cleared. after the voltage at pin v cc has decreased below v vccreshl , the device enters normal operating mode agai n and the internal registers are reset. 3.7 temperature wa rning and shutdown if the junction temperature rises above the temperature warning threshold (t jtw ), a temperature warning flag is set after the temperature warning filter time (t jtft ) and can be read via spi. if the junction temperature increases above the temperature shutdown threshold (t jts ), the thermal shutdown bit is set and the power transistors of all output stages are switched off to protect the device after the thermal shutdown filter time. the gates of the h-bridge are discharged by the ?resistive low? mode. the temperature warning and thermal shutdown flags are latched and must be cleared by the microcontroller. this is done by a read and clear command on an arbitrary register, because both bits are part of the global status register. after these bits have been cleared, the output stages are reactivated. if the temperature is still above the thermal warnin g threshold, the thermal warning bit is set after t jtft . once this bit is set and the temperature is above the temperature shutdown threshold, temperature shutdown is detected after t jtft and the outputs are switched off. therefore the minimum time after which the outputs are switched off after the bits have been cleared in case the temperature is still above the thermo-shutdow n threshold is twice the thermo-warning/- shutdown filter time t jtft . application information L99DZ81EP 32/62 docid023145 rev 2 3.8 inductive loads each half bridge is built by in ternally connected high- and low-side power dmos transistors. due to the built-in reverse diodes of the output transistors, inductive l oads can be driven at the outputs out4 to out6 without external freewheeling diodes. the high-side drivers out7 to out10 are intended to drive resistive loads. therefore only a limited energy (e < 1 mj) can be dissipated by the internal esd-diodes in freewheeling condition. for inductive loads (l > 100 h) an external freewheeling diode connected between gnd and the corresponding output is required. 3.9 open-load detection the open load detection monitors the load curr ent in each activated output stage. if the load current is below the open load detection threshold for at least t fol the corresponding open- load bit is set in the status register. due to mechanical/electrical iner tia of typical loads a short activation of the outputs (e.g. 3 ms) can be used to test the open load status without changing the mechanical/electrical state of the loads. 3.10 overcurrent detection in case of an overcurrent condition, a flag is set in the status register. if the overcurrent signal is valid for at least t foc , the overcurrent flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit. if the overcurrent recovery bit of the output is cleare d, the microcontroller has to clear the status bits to reactivate the corresponding driver. 3.11 current monitor the current monitor output sources a current im age at the current monitor output, which has three fixed ratios of the instantaneous curren t of the selected high-side driver. outputs with a resistance of 500 m ?? and higher have a ratio of 1/2000, except for out8, which has a ratio of 1/6500, and those with a lower resistance one of 1/10000. the si gnal at output cm is blanked after switching on the driver until co rrect settlement of the circuitry. the bits cm_sel<3:0> define which of the outputs are multiplexed to the current monitor output cm. the current monitor output allows a more precis e analysis of the actual state of the load rather than the detection of an open- or over load condition. for example, it can be used to detect the motor state (s tarting, free running, stalled). moreov er, it is possible to control the power of the defroster more precisely by measuring the load current. the current monitor output is enabled after the current-monitor blanking time, when the selected output is switched on. if this output is off, the curr ent monitor output is in high-impedance mode. 3.12 pwm mode of the power outputs each driver has a corresponding pwm enabl e bit, which can be programmed by the spi interface. if the pwm enable bit is set, the output is cont rolled by the logically and- combination of an internally generated pwm signal and the output control bit of the corresponding driver. the pwm-frequency of all outputs can be programmed to either 122 hz of 244 hz typically. the on-duty-cycle is se t by the four 7-bit re gisters, which control one pwm counter each. therefore the maximum on-time is 100% - 1 lsb. docid023145 rev 2 33/62 L99DZ81EP application information 61 1 lsb = 100/128 %. which output uses which corresponding pwm driver can be seen in the spi register definition. when programming a specific duty-cycle, t he output on/off times as well as the slopes must be taken into account. 3.13 cross-current protection the six half-brides of the device are crosscurrent protected by an internal delay time. if one driver (ls or hs) is turned off, the activation of the other driver of the same half bridge is automatically delayed by the cr osscurrent protec tion time. after the crosscurrent protection time is expired the slew-rate lim ited switch-off phase of the driver is changed to a fast turn- off phase and the opposite driver is turned-on with slew-rate limitation. due to this behavior, it is always guaranteed that th e previously activated driver is completely turned off before the opposite driver starts to conduct 3.14 programmable soft-start functi on to drive loads with higher inrush current loads with start-up currents higher than the overcurrent limits (e.g. inrush current of lamps, start current of motors and cold resistance of heaters) can be driven by using the programmable softstart function (i.e. overcurrent recovery mode). each driver has a corresponding overcurrent recovery bit. if this bit is set, the device automatically switches the outputs on again after a programmable recovery time. the duty cycle in overcurrent condition can be programmed by the spi interface to about 12 % or 25 %. the pwm modulated current provides sufficient average current to power up the load (e.g. heat up the bulb) until the load reaches operating condition. the pwm frequency settles at 1.7 khz and 3 khz. the device itself cannot distinguish bet ween a real overload and a non linear load like a light bulb. a real overload condition can only be qualified by time. for overload detection the microcontroller can switch on the light bulbs by setting the overcurrent recovery bit for the first e.g. 50 ms. after cleari ng the recovery bit the output is automatically switched off, if the overload condition remain s. this overcurrent detection procedure has to be followed in order to ma ke it possible to swit ch on the low side driver of a bridge output, if the associated high-side driver has been used in recovery mode before. application information L99DZ81EP 34/62 docid023145 rev 2 figure 13. overcurrent recovery mode 3.15 h-bridge control (d ir, pwmh, bits sd, sds) the pwmh input controls the drivers of th e external h-bridge transistors. the motor direction can be chosen with the direction input (dir), the duty cycle and frequency with the pwmh input. with the spi-registers sd and sds four different slow-decay modes (via drivers and via diode) can be selected using the high side or the low side transistors. unconnected inputs are defined by internal pull-down current. w , / 2 $ ' 8 q o l p l w h g , q u x v k & x u u h q w / l p l w h g , q u x v k & x u u h q w l q s u r j u d p p d e o h u h f r y h u \ p r g h & x u u h q w / l p l w d w l r q * $ 3 * & ) 7 table 24. h-bridge control truth table n control pins control bits failure bits output pin comment dir pwmh hen sd sds cp_low ov uv ds tsd gh1 gl1 gh2 gl2 1xx0xxxxxxxrlrlrlrlh-bridge disabled 2xx1xx10000rlrlrlrlcharge pump voltage too low 3 x x 1 x x 0 x x x 1 rl rl rl rl thermo-shutdown 4xx1xx01000llllovervoltage 5xx1xx00010l (1) l (1) l (1) l (1) short-circuit (1) 6011xx00000lhhlbridge h2/l1 on 7x010000000lhlhslow-decay m ode ls1 and ls2 on 80010100000lhllslow-decay m ode ls1 on docid023145 rev 2 35/62 L99DZ81EP application information 61 3.16 h-bridge driver slew-rate control the rising and falling sl ope of the drivers for the external high-side power-mos can be slew rate controlled. if this mode is enabled the gate of the external high-side power-mos is driven by a current source instead of a low-impedance output driver switch as long as the drain-source voltage over this power-mos is below the switch threshold. the current is programmed using the bits slew<4:0>, which represent a binary number. this number is multiplied by the minimum current step. this minimum current step is the maximum source- /sink-current (i ghxrmax / i ghxfmax ) divided by 31. programming slew<4:0> to 0 disables the slew rate control and the out put is driven by the low-impe dance output driver switch. 91010100000lllhslow-decay m ode ls2 on 10111xx00000hllhbridge h1/l2 on 11x011000000hlhl slow-decay mode hs1 and hs2 on 120011100000llhlslow-decay m ode hs2 on 131011100000hlllslow-decay m ode hs1 on 1. only the half-bridge (low and high-side), in which one mosfet is in short circuit condition is switched off. both mosfets of the other half-bridge remain active and driven by dir and pwmh table 24. h-bridge control truth table (continued) n control pins control bits failure bits output pin comment dir pwmh hen sd sds cp_low ov uv ds tsd gh1 gl1 gh2 gl2 application information L99DZ81EP 36/62 docid023145 rev 2 figure 14. h-bridge gshx slope 3.17 resistive low the resistive output mode protects the L99DZ81EP and the h-bridge in the standby mode and in some failure modes (thermal shut down (tsd), charge pump low (cp_low) and stuck-at-?1? at pin di). when a gate driver ch anges into the resistive output mode due to a failure a sequence is started. in this sequence the concerning driver is switched into sink condition for 32 s to 64 s to ensure a fast swit ch-off of the h-bridge transistor. if slew rate control is enabled, the sink condition is slew-rate controlled. afterwards the driver is switched into the resistive output mode (resistive path to source). 3.18 short circuit detection /drain source monitoring the drain source voltage of each activated external mosfet of the h-bridge is monitored by comparators to detect shorts to ground or battery. if the voltage-drop over the external mosfet exceeds the threshold voltage v scd for longer than the short current detection time t scd the corresponding gate driver switch es the external mosfet off and the corresponding drain source monitoring flag (ds_mon[3:0]) is set. the ds_mon bits have 9 * 6 + [ w & x u u h q w & r q w u r o o h g & x u u h q w & r q w u r o o h g / r z 5 h v l v w l y h 6 z l w f k & r q w u r o o h g 9 ' 6 + [ w * $ 3 * & ) 7 docid023145 rev 2 37/62 L99DZ81EP application information 61 to be cleared through the spi to reactivate the gate drivers. the drain source monitoring has a filter time of typ. 6 s. this monitoring is only active while the corresponding gate driver is activated. if a drain-source monitor event is detected, the corresponding gate-driver remains activated for at maximum the filter time. when the gate driver switches on, the drain-source comparator requires the specified settling time until the drain-source monitoring is valid. during this time, this drain- source monitor event may start the filter time. the threshold voltage v scd can be programmed using the spi. figure 15. h-bridge diagnosis 3.19 h-bridge monito ring in off-mode the drain source voltages of the h-bridge driv er external transistors can be monitored, while the transistors are switched off. if either bi t ol_h1l2 or ol_h2l1 is set to ?1?, while bit hen = ?1?, the h-drivers enter resistive low mode and the drain-source voltages can be monitored. since the pull-up resistance is equal to the pull-down resistance on both sides of table 25. h-bridge ds-monitor threshold diag<1> diag<0> monitoring threshold voltage (typical) 00 v scd1 =0.5v 01 v scd2 =1.0v 10 v scd3 =1.5v 11 v scd4 =2.0v 0 9 v * + 9 6 6 + * / 6 / 9 6 * + 6 + * / 6 / n n * d w h ' u l y h u + 6 * d w h ' u l y h u / 6 ' 6 0 r q l w r u l q j + 6 ' 6 0 r q l w r u l q j / 6 2 / 0 r q l w r u l q j 9 7 k u h v 9 7 k u h v n n * d w h ' u l y h u + 6 * d w h ' u l y h u / 6 ' 6 0 r q l w r u l q j + 6 ' 6 0 r q l w r u l q j / 6 2 / 0 r q l w r u l q j 9 7 k u h v 9 7 k u h v * $ 3 * & ) 7 application information L99DZ81EP 38/62 docid023145 rev 2 the bridge a voltage of 2/3 v s on the pull-up high-side and 1/3 v s on the low side is expected, if they drive a low-resistive inductiv e load (e.g. motor). if the drain source voltage on each of these power-mos is less than 1/6 v s , the drain-source monitor bit of the associated driver is set. in case of a short to ground the drain-source monitor bits of both low-side gate drivers are set. a short to v s can be diagnosed by setting the ?h-bridge ol high threshold (h-olth high)? bit to one. figure 16. h-bridge open-load detection (no open-load detected) figure 17. h-bridge open-load detection (open-load detected) 0 p n n n 9 v 9 v 9 7 9 v ' 6 0 ' 6 0 9 7 9 v 9 v * $ 3 * & ) 7 0 p n n n 2 s h q 9 v 9 7 9 v ' 6 0 ' 6 0 9 7 9 v 9 v * $ 3 * & ) 7 docid023145 rev 2 39/62 L99DZ81EP application information 61 figure 18. h-bridge open-load detection (short to ground detected) figure 19. h-bridge open-load detectio n with h-olth high = ?1? (short to v s detected) 3.20 programmable cro ss current protection both external mosfet transistors in one half-bridge are disabled for the cross-current protection time (t ccp ) after one mosfet inside this halfbridge is switched off to prevent current flowing from the high -side to the low-side mosfet. the cross current protection time t ccp can be programmed by spi using bits copt<3:0>. 0 p n n n * 1 ' 9 7 9 v ' 6 0 ' 6 0 9 7 9 v * 1 ' 6 k r u w 9 v * $ 3 * & ) 7 0 p n n n ' 6 0 ' 6 0 9 7 9 v 6 k r u w 9 v 9 v 9 v 9 7 9 v * $ 3 * & ) 7 application information L99DZ81EP 40/62 docid023145 rev 2 3.21 watchdog the watchdog monitors the c during normal operation within a nominal trigger cycle of 60ms. the watchdog is triggered by toggling the watchdog bit, which restarts the watchdog timer (i.e. content of the watchdog trigger bit ha s to be inverted). if no watchdog bit inversion has been occurred during the watchdog time-out time t wdto the h-bridge drivers switch into resistive-low condition, a ll power outputs are switched off. table 26. cross-current protection time copt<3> copt<2> copt<1> copt<0> min typ max unit 0 0 0 0 150 250 360 ns 0 0 0 1 390 500 670 ns 0 0 1 0 590 750 980 ns 0 0 1 1 800 1000 1280 ns 0 1 0 0 1000 1250 1600 ns 0 1 0 1 1210 1500 1910 ns 0 1 1 0 1420 1750 2220 ns 0 1 1 1 1630 2000 2540 ns 1 0 0 0 1830 2250 2850 ns 1 0 0 1 2050 2500 3120 ns 1 0 1 0 2250 2750 3450 ns 1 0 1 1 2460 3000 3760 ns 1 1 0 0 2660 3250 4100 ns 1 1 0 1 2880 3500 4370 ns 1 1 1 0 3080 3750 4680 ns 1 1 1 1 3200 4000 5000 ns docid023145 rev 2 41/62 L99DZ81EP functional description of the spi 61 4 functional description of the spi 4.1 general description the spi complies with standard st-spi interface version 3.1. its communication is based on a serial peripheral interface structure using csn (chip select not), di (serial data in), do (seria l data out/error) and clk (serial clock) signal lines. 4.1.1 chip select not (csn) the csn input pin is used to select the serial in terface of this device. when csn is high, the output pin (do) is in high impedance state. a low signal wakes up the device and a serial communication can be started. the state when csn is going low until the rising edge of csn is called a co mmunication frame. 4.1.2 serial data in (di) the di input pin is used to transfer data seria lly into the device. the data applied to the di is sampled at the rising edge of the clk signal. a stuck-at ?0? or ?1? enters the standby mode. 4.1.3 serial clock (clk) the clk input signal provides the timing of th e serial interface. the data input (di) is latched at the rising edge of serial clock cl k. the spi can be driven by a micro controller with its spi peripheral running in following mode : cpol = 0 and cpha = 0. data on serial data out (do) is shifted out at the falling edge of the serial clock (clk). the serial clock clk must be active only during a frame (csn lo w). any other switching of clk close to any csn edge could generate set up/hold violations in the spi logic of the device. the clock monitor counts the number of clock pulses du ring a communication frame (while csn is low). if the number of clk pulses does not correspond to the frame width indicated in the functional description of the spi L99DZ81EP 42/62 docid023145 rev 2 this 8-bit register indicates the spi frame length (24 bit) and the availability of additional features. each communication frame consists of a command byte, which is followed by two data bytes. the data returned on do within the same fr ame always starts with the docid023145 rev 2 43/62 L99DZ81EP functional description of the spi 61 4.2 command byte ocx: operation code ax: address dx: data bit each communication frame starts with a command byte. it consists of an operating code which specifies the type of operation ( , |
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